ZHAO Bao-jun, SHI Cai-cheng, BI li, et al. Implementation of Real-Time 2D-DCT with FPGA and DSP[J]. Acta Electronica Sinica, 2003, 31(9): 1317-1319.
DOI:
ZHAO Bao-jun, SHI Cai-cheng, BI li, et al. Implementation of Real-Time 2D-DCT with FPGA and DSP[J]. Acta Electronica Sinica, 2003, 31(9): 1317-1319.DOI:
Implementation of Real-Time 2D-DCT with FPGA and DSP
Because of the FPGA's parallel pipelining processing features
this paper designed and implemented the real time CIF format image DCT using Exilinx Company's 500000 gate grade chip XCV400E.Using ping-pong model
C×F×C
T
is implemented only by designing one fast algorithm model (
F×C
T
).Digital video signal is input to FPGA line by line.Controlling by horizontal sync and vertical sync
every group data of 8 pixels as a vector is inp
ut and is multiplied
C
T
i.e.(
F×C
T
).The computed results are stored as transform format.Each pixel needs one (1×8)×(8×8) matrix operations.Each line needs 352×(1×8)×(8×8) times matrix operations.44times (1×8)×(8×8) matrix operations results need storing as transform format (
H
T
=(F×C
T
)
T
).When next 8 line data are input
they are processed with the same way as the above.For the last 8 line's first processed results (
F×C
T
)
they are read out and processed as (
H
T
×C
T
).The final results are output as transform format (
G
T
=C×H
).Therefore
the continuous real-time whole field pix DCT transform
C×F×C
T
is finished.Function and timing simulation and the successful connection with TMS320C62X system verified the design and implement.