Algorithm and Structure Design of Logarithmic Skip Adder

JIA Song; LIU Fei; LIU Ling; CHEN Zhong-jian; JI Li-jiu

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Algorithm and Structure Design of Logarithmic Skip Adder

更新时间：2025-07-16

- Algorithm and Structure Design of Logarithmic Skip Adder
- Acta Electronica Sinica Vol. 31, Issue 8, Pages: 1186-1189(2003)
- 作者机构：
  
  北京大学微电子研究院,北京,100871
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP342+.21
- Published：2003
- 稿件说明：
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JIA Song, LIU Fei, LIU Ling, et al. Algorithm and Structure Design of Logarithmic Skip Adder[J]. Acta Electronica Sinica, 2003, 31(8): 1186-1189.
DOI：

JIA Song, LIU Fei, LIU Ling, et al. Algorithm and Structure Design of Logarithmic Skip Adder[J]. Acta Electronica Sinica, 2003, 31(8): 1186-1189. DOI：

摘要

本文介绍一种新型加法器结构——对数跳跃加法器

该结构结合进位跳跃加法器和树形超前进位加法器算法

将跳跃进位分组内的进位链改成二叉树形超前进位结构

组内的路径延迟同操作数长度呈对数关系

因而结合了传统进位跳跃结构面积小、功耗低的特点和ELM树形CLA在速度方面的优势.在结构设计中应用Ling's算法设计进位结合结构

在不增加关键路径延迟的前提下

将初始进位嵌入到进位链.32位对数跳跃加法器的最大扇出为5

关键路径为8级逻辑门延迟

结构规整

易于集成.spectre电路仿真结果表明

在0.25μmCMOS工艺下

32位加法器的关键路径延迟为760ps

100MHz工作频率下功耗为5.2mW.

Abstract

LSA (Logarithmic Skip Adder) Algorithm is introduced in this paper.LSA is a hybrid structure of carry skip adder and ELM carry lookahead adder

which replaces serial carry chain with binary tree structure.In structure design

a carry-incorporated structure to include the primary carry input in carry chain is found to reduce logic depth.With its regular structure

32-bit LSA has a logic depth of 8 and a fanout no more than 5.Circuit simulating results in 0.25um CMOS process show a critical path delay of 760ps.

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