The VLSI Implementation of the High Performance Data Path Design in VLIW Processor

YANG Yan; HOU Chao-huan

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The VLSI Implementation of the High Performance Data Path Design in VLIW Processor

更新时间：2025-07-16

- The VLSI Implementation of the High Performance Data Path Design in VLIW Processor
- Acta Electronica Sinica Vol. 31, Issue 11, Pages: 1667-1670(2003)
- 作者机构：
  
  中国科学院研究生院,中国科学院声学所,北京,100080
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP333
- Published：2003
- 稿件说明：
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YANG Yan, HOU Chao-huan. The VLSI Implementation of the High Performance Data Path Design in VLIW Processor[J]. Acta Electronica Sinica, 2003, 31(11): 1667-1670.
DOI：

YANG Yan, HOU Chao-huan. The VLSI Implementation of the High Performance Data Path Design in VLIW Processor[J]. Acta Electronica Sinica, 2003, 31(11): 1667-1670. DOI：

摘要

本文提出一种新的基于VLIW处理器的层次化数据通道的VLSI结构

通过独特的微码结构

十分方便地得到了具有可配置特征的高速数据通道的控制模型

模型能有效地改善系统扩展所需要的灵活性

适合构建高性能的媒体处理器阵列.运用VHDL语言实现的硬件设计通过了系统仿真.100MHz时钟频率下的最大数据吞吐率可达1.28Gbit/s.

Abstract

A novel VLSI architecture of hierarchical data path

based on VLIW core

is presented.Specific microcode structure is employed to exploit high speed and reconfigurable data path model that can efficiently improve the flexibility in system extending.It is also particularly convenient for high performance media processor array implementation.The design was implemented with VHDL and passed system simulation.The maximum data throughput will reach 1.28Gbit/s at 100 MHz system clock.

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