Study on System-Level Power Model for Low Power Optimization

LI Xi; WANG Zhi-gang; ZHOU Xue-hai; WANG Xu-fa

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Study on System-Level Power Model for Low Power Optimization

更新时间：2025-07-16

- Study on System-Level Power Model for Low Power Optimization
- Acta Electronica Sinica Vol. 32, Issue 2, Pages: 205-208(2004)
- 作者机构：
  
  中国科学技术大学计算机系,安徽,合肥,230026
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP302.7
- Published：2004
- 稿件说明：
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LI Xi, WANG Zhi-gang, ZHOU Xue-hai, et al. Study on System-Level Power Model for Low Power Optimization[J]. Acta Electronica Sinica, 2004, 32(2): 205-208.
DOI：

LI Xi, WANG Zhi-gang, ZHOU Xue-hai, et al. Study on System-Level Power Model for Low Power Optimization[J]. Acta Electronica Sinica, 2004, 32(2): 205-208. DOI：

摘要

随着嵌入式系统应用的普及

低功耗设计成为系统设计中的关键问题之一.本文提出了一个两层构架的系统级功耗模型

包括微体系结构层模型和体系结构层模型.微体系结构模型支持系统级硬件结构设计优化

体系结构模型则针对编译器的软件设计优化.微结构模型以部件的结构信息特征为依据

指令级模型以微结构模型为基础.试验证明

该模型可以满足嵌入式系统的高层设计要求.

Abstract

With the popularization of embedded systems

low power design has become one of the most challenging tasks in the embedded system development.This paper presents a novel two-level power estimation model operating at the system-level

which including a microarchitecture level model to support hardware optimization and an instruction level model to support software compiling optimization.The microarchitecture level model based upon the information of components structure.The instruction level model based upon the microarchitecture model.Thus the proposed methodology provides an accurate and rapid model to evaluate embedded system high level design.

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