Study on a Novel Probability Decoder Implemented by Analog LSI

YANG Shu-hui; QIU Yu-lin

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Study on a Novel Probability Decoder Implemented by Analog LSI

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- Study on a Novel Probability Decoder Implemented by Analog LSI
- Acta Electronica Sinica Vol. 32, Issue 2, Pages: 236-240(2004)
- 作者机构：
  
  中国科学院微电子中心,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN919.3+1
- Published：2004
- 稿件说明：
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YANG Shu-hui, QIU Yu-lin. Study on a Novel Probability Decoder Implemented by Analog LSI[J]. Acta Electronica Sinica, 2004, 32(2): 236-240.
DOI：

YANG Shu-hui, QIU Yu-lin. Study on a Novel Probability Decoder Implemented by Analog LSI[J]. Acta Electronica Sinica, 2004, 32(2): 236-240. DOI：

摘要

本文利用工作在亚阈值模式的MOS管特性

设计了一种低功耗的模拟电流型乘法器

并以此乘法器为核心

设计了一组利用电流进行概率计算的模拟单元电路.根据这些单元电路

基于最大后验概率算法(MAP)

实现了(5

3)格码软判决译码的概率解码器.在解码器的输入部分设计了新型的具有流水线结构的串行输入接口.用标准的0.6μm CMOS工艺对解码器进行了性能模拟验证.

Abstract

Using the subthreshold MOS transistors

a low power current-mode multiplier is given in the paper.By adopting the multiplier as the kernel circuit

some modules used to compute the probability are designed.On the bases of these modules and the MAP algorithm

a soft-decision probability decoder of the (5

3) trellis code is implemented

and a novel pipelining serial input interface for the decoder is proposed.To verify the performance

the decoder is simulated with the model of standard 0.6μm CMOS process.

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