Instruction cache consumes a large portion of power in processor.By using this method the number of accesses to both tag and data array of set-associative instruction cache can be significantly reduced.The method takes advantage of the fact that tag can be accessed once per line during sequential execution.And in the idle cycles of the tag memory

the next cache line can be pre-visited so that the cache-hit and way-select information can be obtained ahead of time.This information can be used to chip-deselect the missed data array later.Also way prediction mechanism can be utilized in tag pre-visiting scheme to further reduce the number of accesses to the tag array without performance penalty.A way-select circular history buffer (CHB) is maintained to record way-select information of a cache line.Short branches within the address range of the CHB will not require accessing to the tag array and missed data array.This method has been implemented in a 250 MHz high-performance low-power RISC processor.