Parallel Array VLSI Architecture Design of 2-D DWT for JPEG2000

LAN Xu-guang; ZHENG Nan-ning; MEI Kui-zhi; LIU Yue-hu

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Parallel Array VLSI Architecture Design of 2-D DWT for JPEG2000

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- Parallel Array VLSI Architecture Design of 2-D DWT for JPEG2000
- Acta Electronica Sinica Vol. 32, Issue 11, Pages: 1806-1809(2004)
- 作者机构：
  
  西安交通大学人工智能与机器人研究所,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN406
- Published：2004
- 稿件说明：
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LAN Xu-guang, ZHENG Nan-ning, MEI Kui-zhi, et al. Parallel Array VLSI Architecture Design of 2-D DWT for JPEG2000[J]. Acta Electronica Sinica, 2004, 32(11): 1806-1809.
DOI：

LAN Xu-guang, ZHENG Nan-ning, MEI Kui-zhi, et al. Parallel Array VLSI Architecture Design of 2-D DWT for JPEG2000[J]. Acta Electronica Sinica, 2004, 32(11): 1806-1809. DOI：

摘要

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器

一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波

用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理

在保证同样的精度下

大大减少了运算量和提高了硬件资源利用率

几乎达到100％

加快了变换速度

也减少了电路的规模.该结构对于

N×N

大小的图像

处理速度达到

O(N

/2)

个时钟周期.二维离散小波滤波器结构已经过FPGA验证

并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.

Abstract

A real-time parallel array architecture is proposed to perform the forward and inverse discrete wavelet transform (DWT) by using lifting scheme for the filters recommended in JPEG2000.It consists of two row processors and one column processor.The signals are processed in parallel way.Multiplications are substituted for shift-add operations.The whole architecture is optimized in the pipeline design way to speed up and achieve higher hardware utilization.It performs a decomposition in approximately

clock cycles for an

N×N

image.A compact and independent IP core based on the architecture for JPEG2000 VLSI implementation has been demonstrated in FPGA.

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