CMOS Implementation of RF PLL Frequency Synthesizer

CHI Bao-yong; SHI Bing-xue; WANG Zhi-hua

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CMOS Implementation of RF PLL Frequency Synthesizer

更新时间：2025-07-16

- CMOS Implementation of RF PLL Frequency Synthesizer
- Acta Electronica Sinica Vol. 32, Issue 11, Pages: 1761-1765(2004)
- 作者机构：
  
  清华大学微电子学研究所,北京,100084
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN79+1
- Published：2004
- 稿件说明：
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CHI Bao-yong, SHI Bing-xue, WANG Zhi-hua. CMOS Implementation of RF PLL Frequency Synthesizer[J]. Acta Electronica Sinica, 2004, 32(11): 1761-1765.
DOI：

CHI Bao-yong, SHI Bing-xue, WANG Zhi-hua. CMOS Implementation of RF PLL Frequency Synthesizer[J]. Acta Electronica Sinica, 2004, 32(11): 1761-1765. DOI：

摘要

本论文实现了一个射频锁相环型频率合成器

它集成了压控振荡器、双模预分频器、鉴频鉴相器、电荷泵、各种数字计数器、数字寄存器和控制电路以及与基带电路的串行接口.它的鉴频鉴相频率、输出频率和电荷泵的电流大小都可以通过串行接口进行控制

还实现了内部压控振荡器和外部压控振荡器选择、功耗控制等功能

这些都使得该频率合成器具有极大的适应性

可以应用于多种通信系统中.该锁相环型频率合成器已经采用0.25μm CMOS工艺实现

测试结果表明

该频率合成器使用内部压控振荡器时的锁定范围为1.82GHz~1.96GHz

在偏离中心频率25MHz处的相位噪声可以达到-119.25dBc/Hz.该频率合成器的模拟部分采用2.7V的电源电压

消耗的电流约为48mA.

Abstract

An integrated RF PLL frequency synthesizer is presented.It integrates VCO

dual-modulus prescaler

PFD

Charge-pump

various digital counters

control logic and the series interface with the base-band processor into a single chip.Also the selection of internal VCO or external VCO and power control are implemented to adapt to various applications.The frequency synthesizer has been implemented in 0.25μm CMOS process.The measured results show that the locked range is 1.82GHz-1.96GHz when the internal VCO is selected

the phase noise could reach -119.25dBc/Hz at 25MHz offset from the carrier 1.924GHz.The analog part uses a 2.7V power supply and the consumed current is about 48mA.

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