10.709 Gbit/s CDR Based on Phase Locked Loop

WANG Yong; YAO Hong-ying; WANG Zi-yu

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10.709 Gbit/s CDR Based on Phase Locked Loop

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- 10.709 Gbit/s CDR Based on Phase Locked Loop
- Acta Electronica Sinica Vol. 33, Issue 8, Pages: 1509-1511(2005)
- 作者机构：
  
  北京大学电子学系区域光纤通信网与新型光通信系统国家重点实验室,北京,100871
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN305
- Published：2005
- 稿件说明：
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WANG Yong, YAO Hong-ying, WANG Zi-yu. 10.709 Gbit/s CDR Based on Phase Locked Loop[J]. Acta Electronica Sinica, 2005, 33(8): 1509-1511.
DOI：

WANG Yong, YAO Hong-ying, WANG Zi-yu. 10.709 Gbit/s CDR Based on Phase Locked Loop[J]. Acta Electronica Sinica, 2005, 33(8): 1509-1511. DOI：

摘要

作者采用D-FF触发器、鉴相器和VCO构成的锁相环

研制出了码率为10.709 Gbit/s的时钟数据再生模块.该模块的中心工作码率可在9.5~11 Gbit/s之间设定

锁定带宽Δ

≈110MHz

输入信号幅度

INp-p

80~1600mV

输出信号幅度

D-p-p

≈900mV

输出信号抖动均方根值

D-RMS

≈1.5~1.6ps、抖动峰峰值

D-p-p

≈7~8ps.

Abstract

Using a D-FF

phase comparator and VCO

the authors produced a 10.709 Gbit/s CDR based on PLL.The operating frequency of the CDR can be set within 9.5~11GHz

the lock bandwidth Δ

is about 110 MHz

the amplitude of input signal

INp-p

is 80~1600mV

the amplitude of output data

D-p-p

is about 900mV

the jitter RMS of output data

D-p-p

is 1.5~1.6ps and the peak-to-peak jitter of output data

D-p-p

is 7~8ps.

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