Automatic Error Correcting Hardware Implementation of AES Algorithm

TANG Ming; ZHANG Guo-ping; ZHANG Huan-guo

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Automatic Error Correcting Hardware Implementation of AES Algorithm

更新时间：2025-07-16

- Automatic Error Correcting Hardware Implementation of AES Algorithm
- Acta Electronica Sinica Vol. 33, Issue 11, Pages: 2013-2016(2005)
- 作者机构：
  
  1. 武汉大学计算机学院,湖北,武汉,430079
  2. 武汉数字工程研究所,湖北,武汉,430074
  3. 武汉大学计算机学院湖北武汉,430079
  4. 武汉数字工程研究所湖北武汉,430074
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP309
- Published：2005
- 稿件说明：
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TANG Ming, ZHANG Guo-ping, ZHANG Huan-guo. Automatic Error Correcting Hardware Implementation of AES Algorithm[J]. Acta Electronica Sinica, 2005, 33(11): 2013-2016.
DOI：

TANG Ming, ZHANG Guo-ping, ZHANG Huan-guo. Automatic Error Correcting Hardware Implementation of AES Algorithm[J]. Acta Electronica Sinica, 2005, 33(11): 2013-2016. DOI：

摘要

提出一种AES硬件容错设计可避免攻击者利用在AES设计环节中插入故障位实现攻击.在原有AES硬件设计中加入汉明码纠错电路

能自动纠正同一字节内的所有单比特故障

硬件仿真实验证明

故障发现率接近100%.针对不同AES设计结构和测试点配置对纠错电路的资源及速度进行了分析

实验结果表明我们提出的硬件容错设计有很强的可行性.

Abstract

We propose a fault tolerance AES hardware implementation to prevent attackers from injecting faults in the process of AES design.The design adds Hamming Code error correction circuits into the original AES implementation and it can correct all single-fault in the same byte automatically.Hardware simulation shows that the ratio of fault detection is close to 100%.The results of analyzing of different architecture and configuration of check points certificate that our proposal is very practical.

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