The Design and Implementation of Scaler

LIU Zheng-lin; ZOU Xue-cheng; XIANG Zhu-quan; XIAO Jian-ping; ZHAO Hui-bo; LI Shi-jie

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The Design and Implementation of Scaler

更新时间：2025-07-16

- The Design and Implementation of Scaler
- Acta Electronica Sinica Vol. 34, Issue 1, Pages: 185-188(2006)
- 作者机构：
  
  华中科技大学电子科学与技术系,湖北,武汉,430074
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP391.41
- Published：2006
- 稿件说明：
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LIU Zheng-lin, ZOU Xue-cheng, XIANG Zhu-quan, et al. The Design and Implementation of Scaler[J]. Acta Electronica Sinica, 2006, 34(1): 185-188.
DOI：

LIU Zheng-lin, ZOU Xue-cheng, XIANG Zhu-quan, et al. The Design and Implementation of Scaler[J]. Acta Electronica Sinica, 2006, 34(1): 185-188. DOI：

摘要

定标器(Scaler)是广泛应用于平板显示器系统中的图像缩放引擎

它将不同分辨率的输入图像经缩放后以固定的分辨率输出到平板显示器上.本文首先在分析定标器系统结构的基础上提出了三个时序约束条件

并推导了相应的公式

当满足这三个约束条件时

定标器中的FIFO和行缓冲区不会上溢或下溢

显示帧与输入帧同步

很好地解决了定标器的时序问题.随后介绍了基于双线性插值算法的图像缩放引擎设计

然后用FPGA实现该缩放引擎

并构建测试环境对整个定标器进行逻辑功能验证

最后给出验证的结果.

Abstract

The scaler is widely used in the flat panel displayer (FPD) system

it zooms the input images which have different resolutions to the fixed resolution image.Based on the analysis of the system architecture of scaler chip used in Flat Panel Displayer

three constraints are proposed.When meeting these constraints

the FIFO and the line buffer will neither overflow nor underflow.The display frame will synchronize with the input frame.The simulating result and verification present that the proposed constraints can meet the requirement of system.Then the scaling engine based on bilinear-interpolation algorithm will be introduced.The total design is implemented by using Virtex-II FPGA of XILINX.Finally

the results of system simulation and logic verification are presented.

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