A reconfigurable cipher chip

which can improve the security and flexibility

has good potential to become a vital component in the future security system.However

the throughput of most reconfigurable cipher chips is pretty lower than that of specific purpose chips.How to improve the throughput becomes more and more important.In this paper

based on the analysis about the reconfiguration of the DES

3DES and AES

we propose a reconfigurable architecture

which combines reconfiguration technology with pipeline

parallel structure.We also implement DES

3DES

AES algorithms based on the reconfiguration architecture.The simulations show that the throughput is 7Gbps for DES

2.3Gbps for 3DES and 1.4Gbps for AES under a 110MHz clock.Moreover

the comparison with other current designs shows that the solution proposed in this paper achieves better performance than other solutions

and thus is suitable to the design of reconfigurable cipher chips.