Register file design is very important in high performance processor design. Register Stack and Register Stack Engine are effective ways to improve performance. Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. In this paper

we present our efforts to design and implement register file management mechanism——MTRM (Mapping Table-based Register Management) on EDSMT

which is a kind of SMT architecture based on IA-64. MTRM assigns a Mapping Table for each thread to mapping their logic registers to physic registers

which adds a middle level into Itanium's original rename mechanism. MTRM focused on supporting the effective sharing of registers in an EDSMT processor

using register renaming to permit multiple threads to share a single global register file. Existing hardware is effective at allocating physical registers;it has only limited ability to identify register deallocation points. Compile optimization is considered to deallocate dead registers

while Special Bit and Special Instruction are used as two effective ways. Simulation results indicate that these mechanisms can reduce register deallocation ineffciencies;in particular

on small register files

the best of the schemes attains speedups of up to 2.2 for some applications

and 1.8 on average.