An area-efficient design proposal of a direct digital frequency synthesizer is presented.It adopts the improved hybrid coordinate rotation digital computer (CORDIC) algorithm.By cutting down all of rotational phase decision circuits and multipliers

adjusting rotational phase error

and finishing complicated amplitude amendment with simple shift and addition-subtraction circuits

the proposal can decrease the hardware complexity and reduce the circuit area.The pipeline multilevel loop iteration implementation architecture is adopted for reusing shifting and addition-subtraction components highly.The simulation indicates that the miscellaneous interference of output frequency spectrum is lower than -70dB.And the design has superior speed and resource usage.The VLSI design proposal has been used in a frequency modulation module of the broadband network System on Chip (SoC) platform.