A Verilog-A Behavioral Model for SET Based on the Master Equation Method

LU Gang; WEI Fen-fen

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A Verilog-A Behavioral Model for SET Based on the Master Equation Method

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- A Verilog-A Behavioral Model for SET Based on the Master Equation Method
- Acta Electronica Sinica Vol. 37, Issue 2, Pages: 342-346(2009)
- 作者机构：
  
  西安理工大学电子工程系,陕西,西安,710048
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN32
- Published：2009
- 稿件说明：
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LU Gang, WEI Fen-fen. A Verilog-A Behavioral Model for SET Based on the Master Equation Method[J]. Acta Electronica Sinica, 2009, 37(2): 342-346.
DOI：

LU Gang, WEI Fen-fen. A Verilog-A Behavioral Model for SET Based on the Master Equation Method[J]. Acta Electronica Sinica, 2009, 37(2): 342-346. DOI：

摘要

基于单电子晶体管的主方程算法

在简化Lientschnig的单电子晶体管模型基础上

建立了基于Verilog-A的单电子晶体管行为描述模型

并利用Cadence Spectre 仿真器对该模型进行了验证.通过单电子晶体管逻辑电路的设计和仿真

表明该模型具有合理的精确度

且速度快

为单电子晶体管电路及混合电路的仿真提供了一种有效的方法.

Abstract

Based on the master equation method of single-electron transistor and a simplified Lientschnig’s single-electron transistor (SET) model

this paper presents a Verilog-A behavioral model for SET

and verified by the tool of Cadence Spectre.The model is shown to be reasonably accurate and fast for SET logic circuit simulation.It offers an efficient method for SET circuits and hybrid circuit co-simulation.

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