Low Power and High Performance Zipper CMOS Domino Full-Adder Design in 45nm Technology

WANG Jin-hui; GONG Na; Geng Shu-qin; HOU Li-gang; WU Wu-chen; DONG Li-min

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Low Power and High Performance Zipper CMOS Domino Full-Adder Design in 45nm Technology

更新时间：2025-07-16

- Low Power and High Performance Zipper CMOS Domino Full-Adder Design in 45nm Technology
- Acta Electronica Sinica Vol. 37, Issue 2, Pages: 266-271(2009)
- 作者机构：
  
  1. 北京工业大学集成电路与系统研究室,北京,100022
  2. 河北大学电子信息工程学院,河北,保定,071002
  3. 北京工业大学集成电路与系统研究室北京,100022
  4. 河北大学电子信息工程学院河北保定,071002
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN4
- Published：2009
- 稿件说明：
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WANG Jin-hui, GONG Na, Geng Shu-qin, et al. Low Power and High Performance Zipper CMOS Domino Full-Adder Design in 45nm Technology[J]. Acta Electronica Sinica, 2009, 37(2): 266-271.
DOI：

WANG Jin-hui, GONG Na, Geng Shu-qin, et al. Low Power and High Performance Zipper CMOS Domino Full-Adder Design in 45nm Technology[J]. Acta Electronica Sinica, 2009, 37(2): 266-271. DOI：

摘要

提出了电荷自补偿技术

此技术利用P型多米诺电路动态结点的放电对N型多米诺电路的动态结点充电

并在此技术基础上综合应用双阈值技术和多电源电压技术

设计了新型低功耗、高性能Zipper CMOS多米诺全加器.仿真过程中提出了功耗分布法

精确找到了电荷自补偿技术的最优路径.仿真结果表明

在相同的时间延迟下

与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比

新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7％

静态功耗分别减小了41%

20%和43%.最后

分析并得到了新型全加器漏电流最低的输入矢量和时钟状态.

Abstract

A charge self-compensation techniques

based on the dynamic node of the P-type charging dynamic node of N-type

is proposed in this paper.Utilizing this technique

the dual-threshold voltage techniques and the multiple supply voltages techniques a low power and high performance Zipper CMOS domino full-adder is designed.And a novel method of the power distribution is introduced.With this method

the optimal path of the proposed Zipper CMOS full-adder with the charge self-compensation techniques is found accurately to minimize the power.Simulation results prove that active power of proposed Zipper CMOS full-adder can be reduced by up to 37%

5% and 7%

and static power can be reduced by up to 41%

20% and 43% as compared to the standard

the dual threshold voltage

and the multiple supply Zipper CMOS domino full-adder under similar delay time

respectively.At last

the inputs and clock signals combination sleep state dependent on leakage current characteristics is analyzed and the optimal sleep state is obtained.

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