Hardware-Software Co-Design Flow for Embedded Coarse-Grained Reconfigurable Processor

YU Su-dong; LIU Lei-bo; YIN Shou-yi; WEI Shao-jun

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Hardware-Software Co-Design Flow for Embedded Coarse-Grained Reconfigurable Processor

更新时间：2025-07-16

- Hardware-Software Co-Design Flow for Embedded Coarse-Grained Reconfigurable Processor
- Acta Electronica Sinica Vol. 37, Issue 5, Pages: 1136-1140(2009)
- 作者机构：
  
  清华大学信息科学与技术国家实验室,清华大学微电子所,北京,100084
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP311.52
- Published：2009
- 稿件说明：
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YU Su-dong, LIU Lei-bo, YIN Shou-yi, et al. Hardware-Software Co-Design Flow for Embedded Coarse-Grained Reconfigurable Processor[J]. Acta Electronica Sinica, 2009, 37(5): 1136-1140.
DOI：

YU Su-dong, LIU Lei-bo, YIN Shou-yi, et al. Hardware-Software Co-Design Flow for Embedded Coarse-Grained Reconfigurable Processor[J]. Acta Electronica Sinica, 2009, 37(5): 1136-1140. DOI：

摘要

面向多媒体应用的可重构处理器架构由主处理器和动态配置的可重构阵列(Reconfigurable Cell Array

RCA)组成.协同设计流程以循环流水线和流水线配置技术为基础

采用启发式算法对应用中较大的关键循环进行了软硬件划分

使用表格调度算法实现了任务在RCA上的映射.经过FPGA验证

H.264基准中的核心算法平均执行速度相比于PipeRench

MorphoSys

以及TI DSP TMS320C64X提高了3.34倍.

Abstract

The reconfigurable processor architecture for multimedia application consists of a host processor and a coarse-grained Reconfigurable Cell Array (RCA) as the coprocessor

which can be reconfigured dynamically.The proposed co-design flow is based on loop pipeline and pipelined reconfiguration technologies.Heuristic algorithm is used for hardware-software partition of big kernel loop and a table schedule algorithm for the mapping of task graph.They have been verified in FPGA with some kernels in H.264 baseline.The average speedup is 3.34 times compared with PipeRench

MorphoSys

and TI DSP TMS320C64X.

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