Conventional FPGAs use transistor switch in short range interconnection and bidirectional mid range lines

which would make the interconnection delay grows exponentially with the wire length as the number of Look Up Table(LUT) in CLB increases.In this article

we present an improved high performance routing architecture

whose short

mid and long range lines are improved to make the interconnect resource has a better delay performance when the CLB tends to become larger and contains more programmable logic resource and the area of CLB grows larger

and compare its performance with the conventional FPGA’s routing architecture by modeling and simulation.Through the comparison

we know that using this new architecture

the double lines are average 21.9% faster

the hex lines are average 21.7% faster

and the lone lines are average 4% faster.And this routing architecture has already been used in the FDP2009-2-SOPC FPGA chip

which is designed and taped out by ourselves.And we also have finished the performance test of its routing resources and proved the superiority of our idea.