An FPGA Robust Technology Mapping Method

CHEN Zhi-hui; ZHANG Chun; WANG Ying; WANG Ling-li

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An FPGA Robust Technology Mapping Method

更新时间：2025-07-16

- An FPGA Robust Technology Mapping Method
- Acta Electronica Sinica Vol. 39, Issue 11, Pages: 2507-2512(2011)
- 作者机构：
  
  复旦大学专用集成电路与系统国家重点实验室,上海,201203
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN47
- Published：2011
- 稿件说明：
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CHEN Zhi-hui, ZHANG Chun, WANG Ying, et al. An FPGA Robust Technology Mapping Method[J]. Acta Electronica Sinica, 2011, 39(11): 2507-2512.
DOI：

CHEN Zhi-hui, ZHANG Chun, WANG Ying, et al. An FPGA Robust Technology Mapping Method[J]. Acta Electronica Sinica, 2011, 39(11): 2507-2512. DOI：

摘要

提出一种基于部分TMR和逻辑门掩盖的FPGA抗辐射工艺映射算法FDRMap

以及一个基于蒙特卡洛仿真的并行错误注入和仿真平台.该平台和算法已经应用到复旦大学自主研发的FPGA芯片FDP4软件流程的工艺映射模块.实验结果表明

FDRMap能够在增加14.06%LUT数目的前提下

降低电路的抗辐射关键度32.62%;与单纯采用部分TMR的方法相比

在节省12.23%的LUT数目同时

还能额外降低电路关键度12.44%.

Abstract

A novel radiation-hard FPGA technology mapping method based on partial TMR and logic gate masking and a fast parallel fault injection and Monte Carlo simulation platform are presented.This platform and method have been used in the mapping module which is part of the CAD flow for self-developed FPGA by Fudan University named FDP4.The experimental results show that FDRMap can decrease the circuit fault criticality by 32.62% with the 14.06% area penalty.Comparing to the partial TMR

it decreases the criticality by 12.44% along with reducing the resources by 12.23%.

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