To improve the performance and energy-efficiency of in-order processors

this paper proposes a novel hardware mechanism

pre-execution based on value prediction and instruction reuse(PVPIR).If a load instruction incurs a long-latency cache miss

PVPIR predicts its data value and uses the predicted value to pre-execute the following dependent instructions

including loads that incur long-latency misses

thus improving the performance.To reduce the energy consumption

PVPIR reuses the valid pre-executed results and thus avoids the re-execution of completed instructions.PVPIR also implements a hybrid value predictor which is a combination of stride prediction and address-value delta(AVD) prediction.The predictor only records history value for loads that have incurred long-latency misses

thus gaining good prediction results with little overhead.Experimental results demonstrate that PVPIR improves the performance by 7.5% and 9.2% while decreases the energy consumption by 11.3% and 4.9%

thus improving the energy-efficiency by 17.5% and 12.9%

as compared to Runahead-AVD and iEA

respectively.