The IEEE 1500 standard was proposed to standardize the IP (Intellectual Property) core test interface to transfer test information.But the typical IEEE 1500-compliant test wrapper would lead IP cores into an insecure status during scan shifting.This paper presented a secure test wrapper design for embedded IP cores

which only inserted a CMOS (Complementary Metal Oxide Semiconductor) transmission gate to the test wrapper cell to eliminate the precarious effect to IP cores.Experiments show that the proposed test wrapper not only takes less area overhead and time delay

but also can test the data path and reduce the data transitions at the input port of IP cores

thus decreases the dynamic test power during scan shifting.