Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections

ZHAO Tian-xu; HAO Yue; MA Pei-jun

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Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections

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- Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections
- Acta Electronica Sinica Vol. 30, Issue 11, Pages: 1707-1710(2002)
- 作者机构：
  
  1. 西安电子科技大学微电子所,陕西,西安,710071
  2. 宝鸡文理学院数学系,陕西,宝鸡,721007
  3. 西安电子科技大学微电子所陕西西安,710071
  4. 宝鸡文理学院数学系陕西宝鸡,721007
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN406
- Published：2002
- 稿件说明：
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ZHAO Tian-xu, HAO Yue, MA Pei-jun. Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections[J]. Acta Electronica Sinica, 2002, 30(11): 1707-1710.
DOI：

ZHAO Tian-xu, HAO Yue, MA Pei-jun. Y/R Model of Integrated Circuits Based on the Open Circuit Fault of Interconnections[J]. Acta Electronica Sinica, 2002, 30(11): 1707-1710. DOI：

摘要

在半导体制造业中

IC的成品率和可靠性(Y/R)是倍受关注的两个问题.研究表明它们之间存在着显著的相关性.为了表征这种相关性

本文从缺陷造成互连线开路的机理出发

分析了成品率关键面积和可靠性关键面积

提出了IC成品率与可靠性关系模型.通过模拟实验给出了该模型的有效性验证.

Abstract

Yield and reliability are two problems that are focused on semiconductor manufacturing.The researched results show that there exists a relation between yield and reliability of IC's.In order to describe this correlativity

the yield critical area and the reliability critical area are analyzed based on the mechanism of open circuit of interconnections caused by manufacturing defects

and the model of relation between IC's yield and reliability is presented in this paper.Finally

the validity of this model is shown by computer simulation.

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Related Author

ZHAO Tian-xu

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