The FPGA Design of on Board SAR Real Time Imaging Processor

XIONG Jun-jun; WANG Zhen-song; YAO Jian-ping; SHI Chang-zhen

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The FPGA Design of on Board SAR Real Time Imaging Processor

更新时间：2025-07-16

- The FPGA Design of on Board SAR Real Time Imaging Processor
- Acta Electronica Sinica Vol. 33, Issue 6, Pages: 1070-1072(2005)
- 作者机构：
  
  1. 中国科学院计算技术研究所,北京,100080
  2. 中国科学院研究生院,北京,100039
  3. 中国科学院计算技术研究所北京,100080
  4. 中国科学院研究生院北京,100039
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN957.52
- Published：2005
- 稿件说明：
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XIONG Jun-jun, WANG Zhen-song, YAO Jian-ping, et al. The FPGA Design of on Board SAR Real Time Imaging Processor[J]. Acta Electronica Sinica, 2005, 33(6): 1070-1072.
DOI：

XIONG Jun-jun, WANG Zhen-song, YAO Jian-ping, et al. The FPGA Design of on Board SAR Real Time Imaging Processor[J]. Acta Electronica Sinica, 2005, 33(6): 1070-1072. DOI：

摘要

本文提出了一种用FPGA实现星载合成孔径雷达实时成像处理器的方法

用来实现星载SAR的CS算法(或RMA算法).该实时成像处理器由7片Xilinx公司的商业FPGA实现

其中4片作为并行的处理单元;一片为CS因子的生成单元;一片为SDRAM控制单元;一片为系统的控制单元.该系统将流水处理和并行处理相结合

从而极大的减少了处理时间.同时根据算法各运算对数据的精度要求不同

将浮点运算和定点运算结合在一块

减少了硬件开销.该系统工作在100MHz时

33秒左右能完成16k*16k星载样本点的成像

并对加拿大Radarsat的雷达原始信号进行成像处理

成像质量能达到要求.

Abstract

This paper designs the on board SAR real time imaging processor using seven pieces of Xilinx FPGA

which consists of four parallel process units

one CS factor unit

one SDRAM controller unit and one control unit.The system combines pipeline process and parallel process to reduce process time

also combines fixed-point operation and floating-point operation to reduce hardware resource.This system can make image within 33 seconds when works in 100MHz

and the imaging quality can fit for the requirement by testing with the Radarsat raw data.

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