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1. 国防科技大学计算机学院,湖南,长沙,410073
2. 西安卫星测控中心,陕西,西安,710043
3. 国防科技大学计算机学院湖南长沙,410073
4. 西安卫星测控中心陕西西安,710043
Published:2009
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JI Rong, FENG Ying-jie, ZENG Xian-jun, et al. The Design of a Novel High-Resolution DLL Phase Detector[J]. Acta Electronica Sinica, 2009, 37(8): 1694-1698.
本文从研究静态相位误差对DLL(Delay-Locked Loop)环路的影响入手
基于Hogge和Alexander结构鉴相器
设计了一款用于30相500MHz DLL的新型高精度鉴相器.与传统的线性鉴相器和二进制鉴相器相比
文中提出的新型鉴相器电路既具有理想线性鉴相器的特点
又解决了电荷泵开启死区的问题
消除了电流舵结构的电荷泵因电流失配带来的静态相位误差.对该鉴相器电路进行0.13μm CMOS工艺下的版图实现
版图之后的仿真结果显示:该鉴相器能正确鉴别1ps以上的相位延迟差
鉴相的精度高达0.18°
完全满足设计要求.
In this paper
based on an analysis of the effects of static phase errors on delay-locked loop (DLL)
a novel high-resolution phase detector (PD) in use for a 30-phase 500MHz DLL
is proposed.It incorporates the feature of the Hogge PD with the feature of the Alexander PD.Compared with conventional linear and binary PDs
the proposed PD not only has advantages of a perfect linear PD
but also solves the problem of dead zone in course of charge pump’s switch transition
which exists in linear PDs
and eliminates static phase errors caused by current mismatch in the charge pump.Furthermore
the layout of the proposed PD in a 1.2-V 0.13μm CMOS process is implemented.Finally
the HSPICE post-layout simulation is performed.The simulation results show that the proposed PD can detect the delay difference between two phases no less than 1ps
and achieve the resolution of 0.18 degree.
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