FONT face, Verdana, HE Xiao-wei, et al. Design and Performance Simulation of a 1.5-6 GHz Two-Stage UWB CMOS LNA with Extra Flat Gain and NF[J]. Acta Electronica Sinica, 2010, 38(7): 1668-1672.
DOI:
FONT face, Verdana, HE Xiao-wei, et al. Design and Performance Simulation of a 1.5-6 GHz Two-Stage UWB CMOS LNA with Extra Flat Gain and NF[J]. Acta Electronica Sinica, 2010, 38(7): 1668-1672.DOI:
Design and Performance Simulation of a 1.5-6 GHz Two-Stage UWB CMOS LNA with Extra Flat Gain and NF
<FONT face=Verdana>A two-stage 1.5-6GHz CMOS Low Noise Amplifier(LNA) for Ultra-Wide-Band(UWB) applications is presented. By introducing common-gate(CG) and common-source(CS) stages to obtain broad-band input matching and current mirror to reuse current through a peaking inductor
the proposed LNA has achieved extra flat power gain and Noise Figure(NF). This LNA has been implemented by a 0.18μm standard CMOS process. Post simulation results have indicated that the power gain(S21) achieves 11.45±0.05dB over the wide frequency band of 1.5-5GHz
and NF maintains 5.15±0.05dB from 2GHz to 6GHz with input return loss(S11)-18dB in the entire band. The simulated input-referred third-order intercept point(IIP3) at 5GHz is -7dBm
while the 1dB compression point is -5dBm. It draws 6mA from 1.8V supply and occupies an area of only 0.62mm^2.