This paper presents a new dynamic reconfigurable architecture of the 4×4 integer transforms for the MPEG-4 AVC /H.264 standard.Two novel 2-D direct signal flow graphs of the 4×4 forward and inverse transforms for H.264 are proposed.A dynamic reconfigurable multi-transform architecture without using transpose memory is proposed on the basis of the new SFGs.There are 16 adders (subtractors) in it.Our design is implemented with 0.18um CMOS technology.The optimum clock frequency of the circuit for the multiple transforms is 200MHz which achieves 800Mpixels/s data throughput rate with the area cost of 5140 gates and the power dissipation of 15.64 mW.Under a clock frequency of 100 Mhz

the architecture allows the real-time processing of HDTV 1080P.Compared with the existing architectures

our design is more efficient in terms of area and power dissipation for HDTV application.