Techniques of Leakage Current Optimization Based on Don’t Care Bits in Test Vectors

WANG Wei; HAN Yin-he; LI Xiao-wei; ZHANG You-sheng

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Techniques of Leakage Current Optimization Based on Don’t Care Bits in Test Vectors

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- Techniques of Leakage Current Optimization Based on Don’t Care Bits in Test Vectors
- Acta Electronica Sinica Vol. 34, Issue 2, Pages: 282-286(2006)
- 作者机构：
  
  1. 合肥工业大学计算机与信息学院,安徽,合肥,230009
  2. 中国科学院计算技术研究所先进测试技术实验室,北京,100080
  3. 合肥工业大学计算机与信息学院安徽合肥,230009
  4. 中国科学院计算技术研究所先进测试技术实验室北京,100080
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP391.76
- Published Online：25 February 2006，
  
  Published：2006
- 稿件说明：
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WANG Wei, HAN Yin-he, LI Xiao-wei, et al. Techniques of Leakage Current Optimization Based on Don’t Care Bits in Test Vectors[J]. Acta Electronica Sinica, 2006, 34(2): 282-286.
DOI：

WANG Wei, HAN Yin-he, LI Xiao-wei, et al. Techniques of Leakage Current Optimization Based on Don’t Care Bits in Test Vectors[J]. Acta Electronica Sinica, 2006, 34(2): 282-286. DOI：

摘要

众所周知

CMOS电路测试时由漏电流引起的漏电流功耗在测试功耗中处于重要地位.降低测试时的漏电流对于延长需要周期性自测试的便携式系统电池寿命、提高测试的可靠性和降低测试成本都至关重要.文章首先分析了漏电流的组成

和与之相关的晶体管的堆栈效应.然后

我们提出了一种基于测试向量中不确定位(X位)、使用遗传算法优化集成电路测试时漏电流的方法.实验结果证明在组合电路和时序电路测试中该方法能够在不影响故障覆盖率的条件下

有效优化测试时电路的漏电流.

Abstract

It is well-known that leakage power dissipation caused by leakage current in CMOS circuits during test periods has become a significant part of the total power dissipation.It is important to reduce leakage power to improve battery life in portable systems employing periodic self-test

to increase reliability of test and to reduce test-cost.This paper first analyzes leakage current

and introduces the transistor stacking effect relevant to it.Then

we present a method based on don't care bits (X) in test vectors and using the genetic algorithm to optimize leakage current in IC test.Experimental results indicate that this method can effectually optimize leakage current of combinational circuits and sequential circuits during test

and it doesn't lose fault coverage.

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