Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

WANG Peng-jun; YU Jun-jun

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Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM

更新时间：2025-07-16

- Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM
- Acta Electronica Sinica Vol. 34, Issue 2, Pages: 301-305(2006)
- 作者机构：
  
  宁波大学电路与系统研究所,浙江,宁波,315211
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN712
- Published Online：25 February 2006，
  
  Published：2006
- 稿件说明：
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WANG Peng-jun, YU Jun-jun. Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM[J]. Acta Electronica Sinica, 2006, 34(2): 301-305.
DOI：

WANG Peng-jun, YU Jun-jun. Design of Clocked Transmission Gate Adiabatic Logic Circuit and SRAM[J]. Acta Electronica Sinica, 2006, 34(2): 301-305. DOI：

摘要

本文利用NMOS管的自举效应设计了一种新的采用二相无交叠功率时钟的绝热逻辑电路——钟控传输门绝热逻辑电路

实现对输出负载全绝热方式充放电.依此进一步设计了一种新型绝热SRAM

从而可以以全绝热方式有效恢复在字线、写位线、敏感放大线及地址译码器上的大开关电容的电荷.最后

在采用TSMC 0.25 μ m CMOS工艺器件参数情况下

对所设计的绝热SRAM进行HSPCIE模拟

结果表明

此SRAM逻辑功能正确

低功耗特性明显.

Abstract

A new adiabatic logic circuit adopting two-phase non-overlap power clocks-Clocked Transmission Gate Adiabatic Logic circuit was designed by using the bootstrap effect of NMOS transistors

so that it could charge or discharge output loads in a fully adiabatic manner.Based on this circuit

a novel adiabatic SRAM was designed.So it could recover the charge of large switching capacitances on word-lines

write bit-lines

sense amplified lines and address decoders in a fully adiabatic manner.Using the parameters of TSMC 0.25 μ m CMOS device

the adiabatic SRAM designed was simulated by HSPICE.The simulation results indicate that this SRAM has correct logic function and the character of clearly low power.

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