This paper introduces a two-hierarchy pipeline structure for FIR filters design.It is a flexible ASIC architecture for user specified symbol rate.By adopting the inner clock several times faster than the input data sampling rate

multiplying and adding component can be highly shared to reduce the area.In light of the number of taps of the filter N and the multiple of inner clock frequency to sampling rate M

N/M-1 taps should be added in the chain of taps in this two-hierarchy pipeline architecture

which separate computations into N/M groups.The two hierarchies of pipeline are in-group with M stages and between-group with N/M stages respectively.As the number of taps of filter increases

the structure can be easily extended without increasing the delay of critical path.This method is flexible and can be adopted in other similar application specific filters design.