Dynamical Optimizing High-Speed Clock Tree by Moment Matching Method

WEI Jing-he; CHEN Jun-ning; KE Dao-ming; SHI Long-xing; LU Sheng-li; FANG Jin

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Dynamical Optimizing High-Speed Clock Tree by Moment Matching Method

更新时间：2025-07-16

- Dynamical Optimizing High-Speed Clock Tree by Moment Matching Method
- Acta Electronica Sinica Vol. 32, Issue 9, Pages: 1569-1571(2004)
- 作者机构：
  
  1. 安徽大学电子工程与信息科学系,安徽,合肥,230039
  2. 东南大学电子工程系,江苏,南京,210096
  3. 安徽大学电子工程与信息科学系安徽合肥,230039
  4. 东南大学电子工程系江苏南京,210096
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN454
- Published Online：25 September 2004，
  
  Published：2004
- 稿件说明：
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WEI Jing-he, CHEN Jun-ning, KE Dao-ming, et al. Dynamical Optimizing High-Speed Clock Tree by Moment Matching Method[J]. Acta Electronica Sinica, 2004, 32(9): 1569-1571.
DOI：

WEI Jing-he, CHEN Jun-ning, KE Dao-ming, et al. Dynamical Optimizing High-Speed Clock Tree by Moment Matching Method[J]. Acta Electronica Sinica, 2004, 32(9): 1569-1571. DOI：

摘要

本文讨论如何设计工作在GHz频率下的VLSI芯片时钟电路.时钟树采用平衡平面布局消除时钟偏差;利用插入缓冲器对电路性能进行动态优化.最后用一个电路模拟软件对电路进行评估.和以往的工作相比较

本文实现了在频域内对时钟电路的优化

显著地提高了仿真速度.

Abstract

We discuss the design of clock distribution circuits for VLSI chips operating at GHz frequency.Clock tree uses balanced planar tree routing to eliminate the clock skew;and dynamically optimize clock circuit by inserting buffers.Finally we evaluate the clock circuit performance by simulator.The method realizes the optimization of clock circuit in the frequent domain

and dramatically improve simulating time compared with previous work.

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