VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture

ZHANG Guang-lie; ZHENG Nan-ning; WU Yong; ZHANG Xia

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VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture

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- VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture
- Acta Electronica Sinica Vol. 30, Issue 7, Pages: 945-948(2002)
- 作者机构：
  
  西安交通大学人工智能与机器人研究所,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN941.3
- Published Online：25 July 2002，
  
  Published：2002
- 稿件说明：
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ZHANG Guang-lie, ZHENG Nan-ning, WU Yong, et al. VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture[J]. Acta Electronica Sinica, 2002, 30(7): 945-948.
DOI：

ZHANG Guang-lie, ZHENG Nan-ning, WU Yong, et al. VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture[J]. Acta Electronica Sinica, 2002, 30(7): 945-948. DOI：

摘要

本文在讨论隔行视频信号的逐行处理算法的VLSI实现和视频信号的色度处理和色度空间转换的硬件实现基础上

针对视频信号处理实时性

并发性以及运算量大的特点

提出了基于同步并行流水线的VLSI结构.同时结合SOC的IP模块设计给出相应的硬件实现算法.该设计已基于0.35μm CMOS工艺标准单元库进行了综合验证.

Abstract

This paper describes a novel design method of real time video processing

de-interlacing

color transient improvement and color space conversion

which is suitable for VLSI implementation.A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing.The hardware design based on IP module of SOC is also discussed.This design has been verified by Synopsys EDA tool based on 0.35μm CMOS.

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