Estimation of maximum power dissipation is important in designing highly reliable VLSI systems.However

maximum power estimation for CMOS circuits is essentially a combination optimization problem

which has exponential complexity in the worst case.In this paper

we propose a novel approach to obtain a lower bound of the maximum power dissipation using Genetic Algorithm (GA).Experiments with ISCAS-85 and ISCAS-89 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation-based techniques.In addition

a statistics based technique is realized to serve as a comparison version for our GA approach and to generate a metric to measure the equality of a lower bound from a statistical point of view.