This paper proposes a delay estimation method for different interconnect tree topologies.Using this method

we can incrementally compute transfer function for general interconnection trees and construct a two pole transfer function to approximate the actual transfer function by coefficients matching

not the moment computation

then derive a two pole model for delay estimation.The delay estimates using our method are very close to spice computed delays.And the trade off between accuracy and efficiency can be obtained.It is useful for delay calculation of interconnection in the performance driven synthesis and layout of VLSI routing topologies.