A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller

ZHANG Jian; LAI Zong  sheng; YANG Xian  feng

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A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller

更新时间：2025-12-08

- A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller
- Acta Electronica Sinica Issue 11, (1999)
- 作者机构：
  
  华东师范大学电子系!上海200062
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP273.4
- Published：1999
- 稿件说明：
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[1]张健,赖宗声,杨险峰.一种采用先进流水技术的模糊控制器VLSI结构[J].电子学报,1999(11):109-111.

ZHANG Jian, LAI Zong sheng, YANG Xian feng. A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller[J]. Acta Electronica Sinica, 1999, (11).
[1]张健,赖宗声,杨险峰.一种采用先进流水技术的模糊控制器VLSI结构[J].电子学报,1999(11):109-111. DOI：

ZHANG Jian, LAI Zong sheng, YANG Xian feng. A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller[J]. Acta Electronica Sinica, 1999, (11). DOI：

摘要

本文介绍了一种采用先进流水技术的模糊控制器（FMC）的VLSI结构.该结构的运算采用了单指令流多数据流（SIMD）方式.以及多种先进的流水技术

包括:细分流水、流水的集中式动态调度、超级标量流水等.通过这些技术处理

使每条模糊运算指令平均所需时钟周期数（CPI）=05.基于硬件描述语言（VHDL）的模拟和综合结果表明

采用15μmCMOS工艺库

电路的规模约为20k单元面积（内含2kRAM）.在最坏情况下

最高时钟频率可达30MHz

平均每秒处理模糊规则数（FLIPS）=60M.

Abstract

A specific VLSI design with advanced pipeline architecture for fuzzy micro controller is presented in this paper.It uses way of single instruction flow and multi dataflow（SIMD）

and adopts some advanced structures

including;superscalar pipeline

precontract table

etc.so it has better performances that cycles per fuzzy instruction （CPI） is 0 5.This circuit is simulated by the hardware description language （VHDL）.Synthesis results show that the IC chip contains about 20k unit area （include 2k RAM）

and the average fuzzy logical inference per second（FLIPS） can reach 60M rules/s when 1 5μm CMOS process technology is used.

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