Logic Design of Low Power Double Edge Triggered Flip  Flop

Wu Xunwei; Wei Jian

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Logic Design of Low Power Double Edge Triggered Flip Flop

更新时间：2025-12-08

- Logic Design of Low Power Double Edge Triggered Flip Flop
- Acta Electronica Sinica Issue 5, (1999)
- 作者机构：
  
  1. 浙江大学电子工程系
  2. 美国南加州大学电气工程系统系
  3. 浙江大学电子工程系美国南加州大学电气工程系统系
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN431.202
- Published：1999
- 稿件说明：
移动端阅览
[1]吴训威,韦健.低功耗双边沿触发器的逻辑设计[J].电子学报,1999(05):130-132.

Wu Xunwei, Wei Jian. Logic Design of Low Power Double Edge Triggered Flip Flop[J]. Acta Electronica Sinica, 1999, (5).
[1]吴训威,韦健.低功耗双边沿触发器的逻辑设计[J].电子学报,1999(05):130-132. DOI：

Wu Xunwei, Wei Jian. Logic Design of Low Power Double Edge Triggered Flip Flop[J]. Acta Electronica Sinica, 1999, (5). DOI：

摘要

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能，能够正常地应用于时序电路的设计，并且由于时钟工作频率减半而导致系统功耗的明显降低．

Abstract

To erase the bootless power dissipation of the redundant leap of the clock

this paper proposes the design of DETFF （double edge triggered flip flop） and the logic structure based on NAND gates.PSPICE simulation shows that this type of flip flop has correct logic function and can be normally used in the design of sequential circuits.By using the half working frequency of the clock

power dissipation of the system can be reduced evidently.

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