Design and Hardware Implementation of a High Speed Huffman Decoder

丁保延; 陈亮; 章倩苓

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Design and Hardware Implementation of a High Speed Huffman Decoder

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- Design and Hardware Implementation of a High Speed Huffman Decoder
- Acta Electronica Sinica Issue 11, Pages: 29-32(1998)
- 作者机构：
  
  1. 复旦大学专用集成电路与系统国家重点实验室!上海
  2. 200433
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN762
- Published：1998
- 稿件说明：
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[1]丁保延,陈亮,章倩苓.高速Huffman解码器设计与实现[J].电子学报,1998(11):29-32.

丁保延, 陈亮, 章倩苓. Design and Hardware Implementation of a High Speed Huffman Decoder[J]. Acta Electronica Sinica, 1998, (11): 29-32.
[1]丁保延,陈亮,章倩苓.高速Huffman解码器设计与实现[J].电子学报,1998(11):29-32. DOI：

丁保延, 陈亮, 章倩苓. Design and Hardware Implementation of a High Speed Huffman Decoder[J]. Acta Electronica Sinica, 1998, (11): 29-32. DOI：

摘要

本文设计了一种新的Huffman解码器的算法，它不仅能够减少常规算法对存储空间的要求更为重要的是它能够在一个时钟节拍中处理多个数据，具有明显的优点最后我们以JPEG为例描述了它的VLSI实现方案

Abstract

A new Huffman decoding algorithm is given in this paper

which is not only efficient in memory requirement

but also can speed up the process of decading. The hardware design of JPEG’sHuffman decoder is implemented as an example at last.

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