Yield Prediction and Simulation Technologies of VLSI

Hao Yue; Ma Peijun

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Yield Prediction and Simulation Technologies of VLSI

更新时间：2025-12-08

- Yield Prediction and Simulation Technologies of VLSI
- Acta Electronica Sinica Issue 2, (1999)
- 作者机构：
  
  1. 西安电子科技大学微电子所
  2. 浙江大学ＣＡＤ＆ＧＣ实验室
  3. 西安电子科技大学微电子所浙江大学ＣＡＤ＆ＧＣ实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN47
- Published：1999
- 稿件说明：
移动端阅览
[1]郝跃,林锐,马佩军.VLSI成品率预测与仿真[J].电子学报,1999(02):56-59.

Hao Yue, Ma Peijun. Yield Prediction and Simulation Technologies of VLSI[J]. Acta Electronica Sinica, 1999, (2).
[1]郝跃,林锐,马佩军.VLSI成品率预测与仿真[J].电子学报,1999(02):56-59. DOI：

Hao Yue, Ma Peijun. Yield Prediction and Simulation Technologies of VLSI[J]. Acta Electronica Sinica, 1999, (2). DOI：

摘要

本文建立ＩＣ光刻工艺相关缺陷计算模型和基于ＭｏｎｔｅＣａｒｌｏ统计成品率计算模型．阐述了集成电路功能成品率仿真系统ＸＤＹＥＳ实现，讨论了应用ＸＤＹＥＳ实现功能成品率设计，并给出该系统实用性验证．研究分析表明，其结果与实际结果符合很好．

Abstract

In this paper

the defect and yield computational models associated with IC lithography process have been built by Monte Carlo statistical method.A realizable system of IC functional yield simulator

XD YES

and an approach of yield design are obtained.The applications of XD YES have shown that the calculated results agree with the practical ones.

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