The Research on C40 Based Array Architecture for Image Processing

于慧敏; 姚庆栋

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The Research on C40 Based Array Architecture for Image Processing

更新时间：2025-12-08

- The Research on C40 Based Array Architecture for Image Processing
- Acta Electronica Sinica Issue 7, Pages: 138-143(1998)
- 作者机构：
  
  1. 浙江大学信息与电子工程系!杭州
  2. 310027
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN911.7
- Published：1998
- 稿件说明：
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[1]于慧敏,姚庆栋.基于C40阵列图象处理系统结构的研究[J].电子学报,1998(07):138-143.

于慧敏, 姚庆栋. The Research on C40 Based Array Architecture for Image Processing[J]. Acta Electronica Sinica, 1998, (7): 138-143.
[1]于慧敏,姚庆栋.基于C40阵列图象处理系统结构的研究[J].电子学报,1998(07):138-143. DOI：

于慧敏, 姚庆栋. The Research on C40 Based Array Architecture for Image Processing[J]. Acta Electronica Sinica, 1998, (7): 138-143. DOI：

摘要

本文给出了-基于C40DSP的新颖阵列图象处理系统．该阵列采用了全局互连网络和局部互连网络，构成了一分布式存贮器体系和共享存贮器体系相结合的存贮器体系结构．理论研究表明，阵列处理器的性能有了明显的改善．阵列处理器的最大峰值指标可达：800MFLOPS、4．4BOPS和22．4Gbits／s．

Abstract

In this paper

we describe a novel array image processing architecture

which use a global interconnection networks and local intereonnection netwods for local shared RAM. A distributed memory arehitectme in combination with shod memory is designed with the interconnection networks architecture in the array.The theoretical results show that the performance of the array is improved highly. The array can yields its top performance values: 800 MFLOPS 、4 .4 BOPS 22 .4Gbits/s.

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