There exists a great challenge in real-time implementation of motion estimation algorithms in vided eding because of the huge computatiollal overhead of motion estimation algorithms. A novel low-latency motion estimator architecture by using VLSI compression array is prooped for block matching algorithms in this paper

which can effectively implement full search

especially various hierarchical search algorithms

e. g.three-step search and so on. Compared with traditional accumulation treearchitecture it raises the efficiency further with more area-saving. Based on it

an adaptive block matchingalgorithm and its hardware implementation method are given

which decreases the computing burden ofblock matching to about 1/2～1/4 with a very few hardware penalty and even lower latency.