Capacitance Extraction of the Via Hole Structure Embedded in Multilayered Dielectric Media with Perforated Reference Plane

宋犇; 洪伟

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Capacitance Extraction of the Via Hole Structure Embedded in Multilayered Dielectric Media with Perforated Reference Plane

更新时间：2025-12-08

- Capacitance Extraction of the Via Hole Structure Embedded in Multilayered Dielectric Media with Perforated Reference Plane
- Acta Electronica Sinica Issue 3, Pages: 103-105(1998)
- 作者机构：
  
  1. 东南大学毫米波国家重点实验室!南京
  2. 210096
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN301
- Published：1998
- 稿件说明：
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[1]宋犇,洪伟.多层介质中带有网孔接地板通孔结构的准静态电容参数提取[J].电子学报,1998(03):103-105.

宋犇, 洪伟. Capacitance Extraction of the Via Hole Structure Embedded in Multilayered Dielectric Media with Perforated Reference Plane[J]. Acta Electronica Sinica, 1998, (3): 103-105.
[1]宋犇,洪伟.多层介质中带有网孔接地板通孔结构的准静态电容参数提取[J].电子学报,1998(03):103-105. DOI：

宋犇, 洪伟. Capacitance Extraction of the Via Hole Structure Embedded in Multilayered Dielectric Media with Perforated Reference Plane[J]. Acta Electronica Sinica, 1998, (3): 103-105. DOI：

摘要

本文利用维数缩减技术（DRT）结合直线法（MoL）提取了含网孔接地板的多层介质中通孔结构的准静态电容参数．文中的计算结果与Ansoft软件的计算结果符合较好．而计算所需CPU时间仅为Ansoft的四分之一，内存为二十分之一到三十分之一．

Abstract

Dimension Reduction Technique（DRT）combined with the Method of Lines（MoL）has been used to extract the capacitance of the via hole structure embedded in multilayered dielectric media with perforat ed reference planes.The numerical result given in this paper is in good agreement with that of Ansoft’software

but the CPU time is only a quarter of that of Ansoft’s and memory only one twentieth to one thirtieth of Ansoft’s.

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