A Methodology of Liking High-Level Synthesis andLow-Level Physical Design

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- A Methodology of Liking High-Level Synthesis andLow-Level Physical Design
- Acta Electronica Sinica Issue 2, (1998)
- 作者机构：
  
  北京理工大学ＡＳＩＣ研究所
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN702
- Published：1998
- 稿件说明：
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[1]马聪,颜宗福,马卫国,刘明业.VHDL高级综合与底层物理设计的衔接[J].电子学报,1998(02):71-73.

马聪, 颜宗福, 马卫国, et al. A Methodology of Liking High-Level Synthesis andLow-Level Physical Design[J]. Acta Electronica Sinica, 1998, (2).
[1]马聪,颜宗福,马卫国,刘明业.VHDL高级综合与底层物理设计的衔接[J].电子学报,1998(02):71-73. DOI：

马聪, 颜宗福, 马卫国, et al. A Methodology of Liking High-Level Synthesis andLow-Level Physical Design[J]. Acta Electronica Sinica, 1998, (2). DOI：

本文以ＦＰＧＡ为目标讨论了高级综合与底层物理设计的衔接问题。所构成的系统可实现从ＶＨＤＬ行为级描述到ＦＰＧＡ芯片的自动设计。文中首先分析了实现这种衔接所面临的问题，然后阐明实现的方法并给出若干实例的运行结果。

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