Design of Magnitude Comparator in Switch-Level

Ye Shu

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Design of Magnitude Comparator in Switch-Level

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- Design of Magnitude Comparator in Switch-Level
- Acta Electronica Sinica Issue 5, Pages: 116-118(1998)
- 作者机构：
  
  1.   河南行政学院!郑州
  2.   450002
  3.   郑州大学!郑州
  4.   450052
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP331.2
- Published：1998
- 稿件说明：
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[1]叶姝,韩曙.开关级数字比较器设计研究[J].电子学报,1998(05):116-118.

Ye Shu. Design of Magnitude Comparator in Switch-Level[J]. Acta Electronica Sinica, 1998, (5): 116-118.
[1]叶姝,韩曙.开关级数字比较器设计研究[J].电子学报,1998(05):116-118. DOI：

Ye Shu. Design of Magnitude Comparator in Switch-Level[J]. Acta Electronica Sinica, 1998, (5): 116-118. DOI：

摘要

本文研究了传统的数字比较器电路研究，提出了一类开关级CMOS传输门结构的数字比较器电路，分析了这种电路的设计实现方法．研究表明：和传统的数字比较器电路相比，这种电路具有结构简单，布局规则，运算速度快等优点，有一定的应用研究价值．

Abstract

The traditional method to design a magnitude comparator is studied. A new type of magnitude comparator circuit using CMOS transfer-gate is proposed and analyzed in the switch level. The research results show that

compared with traditional circuit

the new circuit is simpler to design

easier to realize

more regular in layout and faster to operate. So it can be used effectively in digital systems.

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