Selection of Scan Chains in Multiple Scan Testability Design

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- Selection of Scan Chains in Multiple Scan Testability Design
- Acta Electronica Sinica Issue 2, (1997)
- 作者机构：
  
  复旦大学专用集成电路与系统国家重点实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN492
- Published：1997
- 稿件说明：
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[1]叶波,韦和民,郑增钰.多链扫描可测性设计中扫描链的选取[J].电子学报,1997(02):11-15.

叶波, 韦和民, 郑增钰. Selection of Scan Chains in Multiple Scan Testability Design[J]. Acta Electronica Sinica, 1997, (2).
[1]叶波,韦和民,郑增钰.多链扫描可测性设计中扫描链的选取[J].电子学报,1997(02):11-15. DOI：

叶波, 韦和民, 郑增钰. Selection of Scan Chains in Multiple Scan Testability Design[J]. Acta Electronica Sinica, 1997, (2). DOI：

本文提出了多链扫描可测性设计中扫描链的构造方法．根据电路的规模、输人／输出管脚数及测试时间的要求确定扫描链个数，引人临界时间的概念，采用动态编程的方法确定每条链中的扫描触发器．采用该方法，计算速度比传统方法显著提高，同时节省了存储空间．

The methodology of constructing scan chains in a design with multiple scan chains is proposed in this paper. Based on the circuit scale

the number of I/O pins available and the test time required

the number of scan chains is decided. Critical time is introduced

and dynamic programming method is used to locate the flip-flops of every scan chain. Using this algorithm

computing velocity is greatly improved and space is saved.

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