A VLAI Architecture for Forward/Inverse 2D Discrete Wavelet Transform

陈旭昀; 周汀; 闵昊; 章倩苓

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A VLAI Architecture for Forward/Inverse 2D Discrete Wavelet Transform

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- A VLAI Architecture for Forward/Inverse 2D Discrete Wavelet Transform
- Acta Electronica Sinica Issue 2, (1997)
- 作者机构：
  
  复旦大学专用集成电路与系统国家重点实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP332
- Published：1997
- 稿件说明：
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[1]陈旭昀,周汀,闵昊,章倩苓.二维DwT／IDWT处理器的VLSI设计[J].电子学报,1997(02):29-32.

陈旭昀, 周汀, 闵昊, et al. A VLAI Architecture for Forward/Inverse 2D Discrete Wavelet Transform[J]. Acta Electronica Sinica, 1997, (2).
[1]陈旭昀,周汀,闵昊,章倩苓.二维DwT／IDWT处理器的VLSI设计[J].电子学报,1997(02):29-32. DOI：

陈旭昀, 周汀, 闵昊, et al. A VLAI Architecture for Forward/Inverse 2D Discrete Wavelet Transform[J]. Acta Electronica Sinica, 1997, (2). DOI：

摘要

在本文中，我们设计了基于多分辨分析，适合于硬件实现的二维ＤＷＴ和ＩＤＷＴ实时系统．采用了ｔｏｐ－ｄｏｗｎ的ＶＬＳＩ设计方法，用硬件描述语言ＶＨＤＬ，在Ｓｙｎｏｐｓｙｓ系统中进行了验证和综合．综合结果表明：系统的规模为７１４０单元面积，对于四层二维小波变换，数据处理速度约可达到４Ｍｐｉｘｅｌ／ｓ．

Abstract

A VLSI architecture for forward/inverse 2D discrete wavelet transform in realtime applications is presented in this paper. It is designed and verified by the hardware descirption language （VHDL）and is suitable for the hardware implementation. The VHDL of our architecture is synthesized by the Synopsys synthesizer. The synthesized circuits contain 7140 area. The results show that the speed of data processing can reach about 4M pixel/s.

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