Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit

Zhou Yingquan

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Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit

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- Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit
- Acta Electronica Sinica Issue 2, (1997)
- 作者机构：
  
  1. 香港理工大学电子工程系
  2. 中科院计算所ＣＡＤ室
  3. 香港理工大学电子工程系中科院计算所ＣＡＤ室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN710
- Published：1997
- 稿件说明：
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[1]周应权,闵应骅.基于连续校验和的模拟检错电路硬件开销的优化[J].电子学报,1997(02):45-49.

Zhou Yingquan. Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit[J]. Acta Electronica Sinica, 1997, (2).
[1]周应权,闵应骅.基于连续校验和的模拟检错电路硬件开销的优化[J].电子学报,1997(02):45-49. DOI：

Zhou Yingquan. Optimization of Hardware Overhead in Continuous Checksum-Based Analog Error Detection Circuit[J]. Acta Electronica Sinica, 1997, (2). DOI：

摘要

基于连续校验和的模拟电路并发检错与纠错技术，可以用来设计具有容错能力的模拟电路．然而，检错电路的硬件开销在实际应用中是一个不能忽略的问题．本文对此进行了研究．提出了优化硬件开销的第一个算法．在不改变功能电路的前提下，该算法不仅能减少检错电路中无源元件的数目，而且还能减少有源元件的个数．通过对算法进行分析，证明了此算法的可行性和有效性．本文还提出了有关全非零解的概念及其存在性判别条件，作为该算法的理论基础。

Abstract

This paper addresses the hardware overhead issue in the continuous checksumbased technique to design fault-tolerant linear analog circuits

and proposes the first optimization algorithm for hardware overhead in the error detection circuit of the checker. Without changing the original circuit

the proposed algorithm can not only reduce the number of passive elements

but also the number of analog operators so that the error detection circuitry in the checker has optimal hardware overhead. The algorithm is proved to be feasible and effective.

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