Design and Performance Analysis of PLL Frequency Syntyesizer with a Charge Pump

沈连丰; 万山; 魏慧海

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Design and Performance Analysis of PLL Frequency Syntyesizer with a Charge Pump

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- Design and Performance Analysis of PLL Frequency Syntyesizer with a Charge Pump
- Acta Electronica Sinica Issue 2, (1997)
- 作者机构：
  
  东南大学“移动通信”国家重点实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN74
- Published：1997
- 稿件说明：
移动端阅览
[1]沈连丰,万山,魏慧海.电荷泵数字锁相环频率合成器的设计及性能分析[J].电子学报,1997(02):122-124.

沈连丰, 万山, 魏慧海. Design and Performance Analysis of PLL Frequency Syntyesizer with a Charge Pump[J]. Acta Electronica Sinica, 1997, (2).
[1]沈连丰,万山,魏慧海.电荷泵数字锁相环频率合成器的设计及性能分析[J].电子学报,1997(02):122-124. DOI：

沈连丰, 万山, 魏慧海. Design and Performance Analysis of PLL Frequency Syntyesizer with a Charge Pump[J]. Acta Electronica Sinica, 1997, (2). DOI：

摘要

本文对电荷泵数字锁相环频率合成器提出一种全新的时域分析法，该方法对这类合成器的设计和改进提供了理论指导，ＣＡＡ软件已被应用于实际．

Abstract

A new analysis method based on time domain is presented for PLL frequency synthesizer with a charge pump and a digital phase-comparator. This method is used to design and improve this kind of synthesizer. CAA software has been applied to practice.

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