An Analysis of Passive Nonlinear Delay Locked Protection Circuit

Yang Shizhong; Wu Yongxiang; Tang Chaowei; Fei Huaipu(Chongqing University; Chongqing 630044)

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An Analysis of Passive Nonlinear Delay Locked Protection Circuit

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- An Analysis of Passive Nonlinear Delay Locked Protection Circuit
- Acta Electronica Sinica Issue 4, (1996)
- 作者机构：
  
  1.   杨士中
  2.   吴永祥
  3.   唐朝伟
  4.   费怀璞
  5.   重庆大学
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN914.4
- Published：1996
- 稿件说明：
移动端阅览
[1].无源非线性延迟锁定保护电路的分析[J].电子学报,1996(04):66-72.

Yang Shizhong, Wu Yongxiang, Tang Chaowei, et al. An Analysis of Passive Nonlinear Delay Locked Protection Circuit[J]. Acta Electronica Sinica, 1996, (4).
[1].无源非线性延迟锁定保护电路的分析[J].电子学报,1996(04):66-72. DOI：

Yang Shizhong, Wu Yongxiang, Tang Chaowei, et al. An Analysis of Passive Nonlinear Delay Locked Protection Circuit[J]. Acta Electronica Sinica, 1996, (4). DOI：

摘要

本文提出一种简单的无源非线性延迟锁定保护电路。它除具有由复杂的数字逻辑电路构成的计数式延迟锁定保护电路的功能外，对实际工程上常用的ｒｃ低通电路相关处理情况，还优于后者。本文分析了无源非线性延迟锁定保护电路的性能，给出了理想积分和ｒｃ低通电路相关处理两种情况下的锁定保持时间的均值和方差。奠定了这种保护系统的理论基础

Abstract

In this paper a simple passive nonlinear delay locked protection circuit is proposed.It posseses all the functions of counter delay locked protection circuit which consists of complex digital logical circuit.Besides

in some cases it’s better than the latter such as in circumstance using rc-lowpass circuit to replace the integrate-dump circuit.The performance of passive nonlinear delay locked protection circuit is analyzed. The mean and variance of locked hold time are given under the conditions of both ideal integration and rc-lowpass circuit correlation processing.

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