On Hardware Implementation of VLSI Mask Verification Algorithms

恽峰; 宗华; 闵昊; 童家榕; 唐璞山

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On Hardware Implementation of VLSI Mask Verification Algorithms

更新时间：2025-12-08

- On Hardware Implementation of VLSI Mask Verification Algorithms
- Acta Electronica Sinica Issue 2, (1996)
- 作者机构：
  
  1. 复旦大学电子工程系ＣＡＤ研究室
  2. 复旦大学ＡＳＩＣ与系统重点实验室
  3. 复旦大学电子工程系ＣＡＤ研究室复旦大学ＡＳＩＣ与系统重点实验室
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN470.2
- Published：1996
- 稿件说明：
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[1]恽峰,宗华,闵昊,童家榕,唐璞山.VLSI版图验证算法的固化研究[J].电子学报,1996(02):32-36.

恽峰, 宗华, 闵昊, et al. On Hardware Implementation of VLSI Mask Verification Algorithms[J]. Acta Electronica Sinica, 1996, (2).
[1]恽峰,宗华,闵昊,童家榕,唐璞山.VLSI版图验证算法的固化研究[J].电子学报,1996(02):32-36. DOI：

恽峰, 宗华, 闵昊, et al. On Hardware Implementation of VLSI Mask Verification Algorithms[J]. Acta Electronica Sinica, 1996, (2). DOI：

摘要

ＶＬＳＩ电路芯片集成度的不断增加，使得设计趋于复杂化，这就对版图验证工具的处理能力与性能提出了进一步的要求。运用特殊的硬件将版图验证的某些算法固化，利用其中内在的并行性来获得处理速度的提高是一类非常有效的方法。本文提出了一种用于在版图验证算法中得到广泛运用的线扫描算法中边排序操作的硬件实现。并且在ＦＰＧＡ上进行了验证，整个系统实现于一块ＰＣ机的扩展卡上。测试的结果表明，对于排序的操作，硬件实现的速度要比软件快一个数量级。

Abstract

The growth in chip densities threatens the effectiveness of today’s mask verification tools with prohibitive.runtime.This paper investigates a new architecture to accelerate VLSI mask checking and presents a hardware implementation of the edge sorting operation used in the scanline algorithm.The whole system is implemented on a print circuit board which can be inserted into one of the slots of the personal computers.The testing results show that the hardware can offer speedup of one magnitude.

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