Design and Development of  TFD SOI Gate Array

魏丽琼; 张兴; 李映雪; 王阳元

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Design and Development of TFD SOI Gate Array

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- Design and Development of TFD SOI Gate Array
- Acta Electronica Sinica Issue 2, (1996)
- 作者机构：
  
  北京大学微电子所
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN451.02
- Published：1996
- 稿件说明：
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[1]魏丽琼,张兴,李映雪,王阳元.薄膜全耗尽SOI门阵列电路设计与实现[J].电子学报,1996(02):46-49.

魏丽琼, 张兴, 李映雪, et al. Design and Development of TFD SOI Gate Array[J]. Acta Electronica Sinica, 1996, (2).
[1]魏丽琼,张兴,李映雪,王阳元.薄膜全耗尽SOI门阵列电路设计与实现[J].电子学报,1996(02):46-49. DOI：

魏丽琼, 张兴, 李映雪, et al. Design and Development of TFD SOI Gate Array[J]. Acta Electronica Sinica, 1996, (2). DOI：

摘要

在Ｄａｉｓｙ系统上设计出通用性强、使用方便的ＳＯＩ门阵列母版及门阵列电路，并采用１．５μｍＣＭＯＳ／ＳＯＩ工艺在薄膜全耗尽ＳＩＭＯＸ材料上得以实现，其中包括多种分频器电路和环形振荡器，环振可工作在２．５Ｖ，门延迟时间在５Ｖ时为４３０ｐｓ。

Abstract

SOI gate array is designed in Daisy Design System and developed on thin film fully depleted SIMOX materials in 1.5μm CMOS/SOI technology.Some frequency dividers and ring oscillators are built on it.The propagation delay time is 430ps.We find that the gate array can work perfectly at Vdd=2.5V.

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