A Very Efficient VLSI Architecture for Motion Estimation Algorithms

舒清明; 徐葭生

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A Very Efficient VLSI Architecture for Motion Estimation Algorithms

更新时间：2025-12-08

- A Very Efficient VLSI Architecture for Motion Estimation Algorithms
- Acta Electronica Sinica Issue 5, (1995)
- 作者机构：
  
  清华大学微电子学研究所
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN919.8
- Published：1995
- 稿件说明：
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[1]舒清明,徐葭生.一种高效地实现运动估计算法的VLSI结构[J].电子学报,1995(05):12-16.

舒清明, 徐葭生. A Very Efficient VLSI Architecture for Motion Estimation Algorithms[J]. Acta Electronica Sinica, 1995, (5).
[1]舒清明,徐葭生.一种高效地实现运动估计算法的VLSI结构[J].电子学报,1995(05):12-16. DOI：

舒清明, 徐葭生. A Very Efficient VLSI Architecture for Motion Estimation Algorithms[J]. Acta Electronica Sinica, 1995, (5). DOI：

摘要

本文提出了一种全新的低延滞、高吞吐率、可编程的ＶＬＳＩ树型结构，它能十分有效地实现ＦＳＡ和ＴＳＳＡ运动估计算法，该结构比其它树型结构少１／３的处理单元（ＰＥ），而且ＰＥ单元的延时减少一半。独特的ＭＥ窗缓冲结构使Ｉ／Ｏ带宽和Ｉ／Ｏ管脚大大减小，交叉流水线技术使硬件利用率可达到１００％，这些特点使得该结构适合ＶＬＳＩ实现。

Abstract

A novel low latency and high throughput programmable tree architecture is proposed

which can efficiently implement both FSA and TSSA algorithms in motion estimation. In the proposed architecture

the processing elements （PE） are reduced by 1/3 and the delay time of PE is decreased by a half compared to other architectures. Specific buffering structure （ME window） is employed to lower I/O bandwidth and decrease I/O pin count. Pipeline interleaving technique is employed to use the hardware 100%. Owing to these properties

the achitecture is very suitable for VLSI implementation.

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